In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, and so forth, the processing, storage, and retrieval of information is coordinated with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. A continual demand exists for devices with higher data rates; consequently, circuit designers have begun to focus on ways to increase the frequency of the clock signal. In SDRAMs, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. The delay between a rising edge of the system clock (external to the SDRAM) and the appearance of valid data at the output of the memory circuit is known as the clock access time of the memory. A goal of memory circuit designers is to minimize clock access time as well as to increase clock frequency.
One of the obstacles to reducing clock access time has been clock skew, that is, the delay time between the externally-supplied system clock signal and the signal that is routed to the memory's output circuitry. This skew in the clock signal internal to the integrated circuit is caused by the delays incurred in the signal passing through the clock input buffer and driver and through any associated resistive-capacitive circuit elements. One solution to the problem of clock skew is the use of a synchronous mirror delay as described by T. Saeki, et al. in "A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay," IEEE Journal of Solid-State Circuits, vol. 31, No. 11, November, 14, 1996, pp. 1656-1665, and also by T. Saeki, et al. in "A 2.5 ns Clock Access 250 MHz 256 Mb SDRAM with a Synchronous Mirror Delay," 1996 IEEE International Solid-State Circuits Conference, pp. 374-375. The synchronous mirror delay (SMD) is a digital circuit that consists of two delay circuit arrays and one control circuit. The SMD detects the clock cycle from two consecutive pulses, generates a clock-synchronized delay, and eliminates the clock skew, all within two clock cycles.
One problem with the synchronous mirror delay approach is that the delay circuit arrays used to measure and then eliminate clock skew are serially-coupled NAND gates and inverters. The output of one NAND gate drives the input of the next NAND gate (through the inverter). Indeed, the prior art SMD is configured such that the output of each NAND gate drives the same input of the successive NAND gate. In other words, the NAND gates have first and second inputs, and the output of the preceding NAND gate is always connected to the first input of the succeeding NAND gate, for example. Since the same input is driven throughout the chain of NAND gates, any asymmetry in the NAND gate is magnified when the signal reaches the end of the series. Thus, the propagation times of signals through the series logic may be different depending upon which input of the multiple input logic gates are cascaded. The difference in propagation time might be large enough that the signal pulse eventually disappears by over-running itself or by simply dissipating because not enough signal strength exists to keep it going. Aspects of the inventive concepts address these problems.